Embedded HardCopy Blocks harden standard or logic-intensive applications, increasing integration and delivering twice the density without a cost or power penalty. The devices also feature some unique features. In August 2011, Altera began shipping 28-nm Stratix V GT devices featuring 28-gigabits-per-second (Gbps) transceivers. This device family has more than 1 million logic elements, up to 53 Mb of embedded memory, up to 7 x72 DDR3 DIMMs at 800 MHz, 1.6-Gbit/s LVDS performance, and up to 3,680 variable-precision DSP blocks. In April 2010, Altera introduced the FPGA industry's second 28-nm device, the Stratix V FPGA (to Xilinx's Kintex-7 FPGA), available with transceivers at speeds up to 28 Gbit/s. These techniques and technologies bring enhancements to device performance and power efficiency. Altera's devices are manufactured using techniques such as 193-nm immersion lithography and technologies such as extreme low-k dielectrics and strained silicon. Semiconductors manufactured on a 40-nm process node address many of the industry's key challenges, including power consumption, device performance, and cost. Since then, the company has also introduced Stratix IV GT FPGAs, which have 11.3-Gbit/s transceivers for 40G/100G applications, and Arria II GX FPGAs, which have 3.75-Gbit/s transceivers for power- and cost-sensitive applications.
Both devices are available with integrated transceiver options.
In May 2008, Altera introduced the industry's first 40-nm programmable logic devices: the Stratix IV FPGAs and HardCopy IV ASICs. Altera's HardCopy Design Center manages test insertion.
Design engineers can employ a single RTL, set of intellectual property (IP) cores, and Quartus II design software for both FPGA and ASIC implementations. The flow has been benchmarked to deliver systems to market 9 to 12 months faster, on average, than with standard-cell solutions. The unique design flow makes hardware/software co-design and co-verification possible.
Design engineers can prototype their designs in Stratix series FPGAs, and then migrate these designs to HardCopy ASICs when they're ready for volume production. This design flow reduces design security risks as well as costs for higher volume production. ASICsĪltera offers a design flow based on HardCopy ASICs, which transitions the FPGA design, once finalized, to a form which is not alterable. Arria FPGAs have integrated transceivers up to 10 Gbit/s. In between these two device families are Arria series FPGAs and SoC FPGAs, which provide a balance of performance, power, and cost for mid-range applications such as remote radio heads, video conferencing equipment, and wireline access equipment. Cyclone series FPGAs and SoC FPGAs are the company's lowest cost, lowest power FPGAs, with variants offering integrated transceivers up to 5 Gbit/s.
The Stratix series FPGAs are the company's largest, highest bandwidth devices, with up to 1.1 million logic elements, integrated transceivers at up to 28 Gbit/s, up to 1.6 Tbit/s of serial switching capability, up to 1,840 GMACs of signal-processing performance, and up to 7 x72 DDR3 memory interfaces at 800 MHz.